CLUSTERED MULTI-PORTED REGISTER FILE WITH BUILT-IN-SELF- TEST CIRCUTRIES IN 90nm CMOS TECHNOLOGY

Requirement on number of register file (RF) ports in parallel processors poses a stringent challenge on RF design. Access time, power consumption and silicon area of the RF are strongly related to the micro-architecture and the number of access ports. A clustered register file with global registers is presented in this paper. Circuit techniques and scheduling sequences are also presented to enhance the testability of the proposed clustered register file. Power consumption and occupied silicon area are reduced due to less wire loading in the clustered architecture. Port-emulation, distributed sequence and circular utilization for enhanced testability are presented in this work. These techniques shorten test length with low area and power overhead. Overall capacity of register files is 256 words x 32 bits, with 8 read ports and 4 write ports. 67% area reduction and 54% power consumption reduction are achieved compared to centralized register file architecture. Test length reduces at lest 67% with proposed techniques. Based on TSMC 90nm CMOS technology, area and power overhead of the BIST circuits are less than 2% and 1%, respectively.